Strained Silicon On Insulator Wafers

This gives rise to a highly nonequilibrium laser process and can vary significantly to that in normal bulk silicon substrate.

Strained silicon on insulator wafers. Semiconductor wafer direct bonding combined with mechanical grinding of the donor wafer and chemical etching of the remaining silicon as well as the sige layer is an alternative to the hydrogen induced layer transfer hilt. For both structures the silicon will be strained in tension by a so called virtual substrate i e. For mosfets applications this new technology. Recently obtained sige free strained silicon on insulator by transferring strained si grown on relaxed sige buffer layers onto an oxide layer 3.

In combination with modified insulator layers also improvements of the electrical properties and optimized. The strained silicon sige substrate and silicon on insulator soi system comprises a thermal insulating layer which prevents a good thermal dissipation pathway. This process allows a larger window for thermal treatments. The virtual substrate was bonded to an oxidized silicon wafer.

The process starts with a virtual substrate having a thin strained silicon layer grown on top of a thick sige buffer. The thicknesses of the si sige stacks are ranging from 40 to 80 nm hence suited to partially depleted soi architectures while. In the second case the strained si layer is placed between the si 1 x ge x layer and the buried oxide which leads after selective etching of the sige layer to a strained silicon on insulator wafer ssoi fig. Si 0 83 ge 0.

This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the smart cut tm technology can be used to obtain good quality tensile. A si 0 0 1 wafer containing relaxed sige today usually.